Interlayer dielectric (ILD) layers are formed between adjacent transistor gates to provide electrical insulation between the adjacent transistor gates. During a manufacturing process, e.g., a gate last process, the ILD layers are subjected to multiple etching, planarizing and cleaning processes, which can damage the ILD layers and form cavities in the ILD layer. In some instances, during metallization processes the cavities become filled with conductive material which reduces the electrical insulation provided by the ILD layers.
The reduced electrical insulation can lead to short circuits between a source/drain of a transistor and the conductive materials filling the cavities in the ILD layers. In some instances, the short circuits render a semiconductor device inoperable or irreparably damage surrounding circuits.